Energy consumption is often recognized as one of the most important parameters in designing modern portable electronic and wireless systems in today's very large scale integration (VLSI) circuit design. Among the various low power techniques at different levels of abstraction, dynamic voltage scheduling (DVS) is an often used technique for reducing power and energy consumption during system operation. DVS aims at reducing the dynamic/static power consumption by scaling down operational frequency and circuit supply voltage. In has been demonstrated that dynamic energy savings can be accomplished by simultaneously varying the supply voltage (Vdd) and the threshold voltage (Vt) through adaptive body biasing. Several researches have been performed to solve task-scheduling on DVS-enabled systems to achieve dynamic energy reduction. For example, heuristics have been proposed for periodic tasks in a multiprocessor.
Research to-date on energy consumption has also increasingly focus on leakage energy. As device sizes continue to decrease due to advances in technological manufacturablity, leakage energy dissipation is becoming more and more important. For the 70-nm process, leakage power is smaller than dynamic power, for the 50-nm process, they become comparable, while for the 35-nm process, leakage power is larger than dynamic power. Hence, it is often predicted that in less than a decade, leakage power will dominate in any energy consumption consideration.
However, low power research has traditionally focused on a power model where the relationship between power consumption and processor speed is convex. Convexity has a number of ramifications when energy is minimized using variable voltage strategies. Chief among them may be the assumption that with respect to energy consumption, it is optimal to execute a task with the executing processor operating at a constant speed. However, the union of several technological, integrated circuits, architectural, operating systems, and application factors is increasingly creating systems where the mapping from the speed of execution (that is the inverse of the time required to complete one cycle and execute an operation) and energy consumption per operation (ES) is non-convex. Non-convex energy-speed models will dominate the wide spectrum of pending and future energy-sensitive systems. For example, in heterogeneous multiprocessor multicore system-on-chips, different cores have different ES functions and the overall relationship between processor speed and energy per operation is not convex. Likewise, total leakage and dynamic energy does not have a convex relationship with processor speed, as leakage current increases when threshold voltage is lowered to increase the processor speed. Incorporation of new high bandwidth on-chip interconnect technologies, such as nanowires, RF, photonic crystals-based optical interconnect, and plasmonics communication networks compounded with a need for thermal management will have further ramifications on the non-convex ES relationship. Instruction level parallelism and effective speed also has a highly non-convex and non-continuous function. Hence, simplified convex energy models assumed in traditional approaches for tackling DVS problem may no longer be effective.
Attempts have been made to develop non-convex methods to achieve energy consumption reduction. DVS techniques in the presence of discrete voltage levels for quadratics power models have been proposed. However, the present disclosure identified that a number of these approaches do not appear optimal and are complex, requiring substantial computing. Further, the present disclosure appreciates that scaling the supply voltage in order to reduce the power consumption has a side-effect on the circuit delay and hence the operational frequency. Each time a processor's supply voltage is switched, the change requires a certain amount of extra energy and time. Thus, the present disclosure identifies that transition overhead is another important issue that should be considered, but has been ignored in conventional voltage scaling techniques.